Mega Projects

Very Large Scale Integration (VLSI) Program
The VLSI Program is jointly implemented by the Japanese Ministry of International Trade and Industry (MITI) and five large companies that produce computers, including Fujitsu, Hitachi, Mitsubishi, Nippon Electric (NEC) and Toshiba. The government and companies share a part of the cost. The research team, Very Large Scale Integration Technology Research Association, is led by the Institute of Integrated Electronic Technology of the Ministry of International Trade and Industry, and is formed jointly with five companies. They established a joint research institute as well.
# Time Title Contents
1 March 1976 VLSI Plan initiated.
2 March 1980 VLSI Plan completed.
VLSI is considered as a classic model for laying the foundation for the competitiveness of the Japanese semiconductor industry, and had major impact on the development of research and development in other countries. The VLSI innovation model has not only become the imitating example of catch-up countries, but also became an example for developed countries to follow. All these countries imitate its innovation model, especially in the experience of establishing a technological innovation system that combines production, academy and research with enterprises as the mainstay, so as to effectively improve national independent capability of innovation.
# Contents Photos
1 A breakthrough was made in high-precision machining technology to significantly increase chip integration
2 The problem of large diameter of silicon wafer was solved
3 Technical issues such as the design, fabrication processing, inspection and evaluation, and device design of LSI and VLSI were solved.
6.

Project Photos

    (source : https://www.sohu.com/a/229710445_466843)
7.

Project Videos

    (source : https://www.youtube.com/watch?v=fwNkg1fsqBY)
# Contents Photos
1 Japan's successful example of catching up with the United States: VLSI Research Program (VLSI, 1976–1980) https://www.sohu.com/a/229710445_466843

[1] Tirumalasetty V R , Machupalli M R . Design and Analysis of Low Power High Speed 1-Bit Full Adder Cells for VLSI Applications[J]. International Journal of Electronics, 2018.

[2] Panda A K , Ray K C . Modified Dual-CLCG Method and Its VLSI Architecture for Pseudorandom Bit Generation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, PP(99):1-14.

[3] Weste N H E, Eshraghian K. Principles of CMOS VLSI design : a systems perspective[M]// Principles of CMOS VLSI design: a systems perspective. 1985.

[4] Najm, F.N. A survey of power estimation techniques in VLSI circuits[J]. IEEE Transactions on Very Large Scale Integration Systems, 2002, 2(4):446-455.

[5] Kung,H T, Leiserson C E. Systolic Arrays for (VLSI).[J]. Proc Sparse Matrix Conf, 1978:256-282.